1. Field of the Invention
The present invention relates to an active matrix substrate and a display device. More specifically, the present invention relates to an active matrix substrate in which a thin film transistor for drive control of a liquid crystal layer and a storage capacitor element are disposed in every pixel, and also relates to an active matrix liquid crystal display device.
2. Description of the Related Art
Active matrix substrates have been widely used in active matrix display devices such as a liquid crystal display device and an EL (Electro luminescence) display device. In conventional active matrix liquid crystal display devices, a switching element such as a TFT (Thin Film Transistor) is disposed at every intersection of a plurality of scanning signal lines with a plurality of data signal lines disposed to intersect with each other on a substrate, and an image signal is transmitted to every pixel by a switching function of the switching element. Further, a storage capacitor element disposed at every pixel is disclosed (for example, refer to, Japanese Kokai Publication No. Hei-06-95157, hereinafter referred to as Patent Document 1). Such a storage capacitor element prevents deterioration of the image signal due to self-discharge of a liquid crystal layer when the TFT and the like is in OFF-state or an OFF-state current of the TFT and the like. The storage capacitor element is used for not only maintaining the image signal when the TFT and the like is in OFF-state, but also as a pathway for application of various modulation signals in liquid crystal driving. Liquid crystal display devices including such a storage capacitor element can permit both low power consumption and high image quality.
One example of a structure of a conventional active matrix substrate is mentioned with reference to drawings.
FIG. 16 is a planar view schematically showing a configuration of one pixel of a conventional active matrix substrate including a storage capacitor element.
In FIG. 16, a plurality of pixel electrodes 51 are formed on an active matrix substrate in a matrix pattern. Around these pixel electrodes 51, a scanning signal line 52 for supplying a scanning signal and a data signal line 53 for supplying a data signal are formed to intersect with each other. At the intersection of the scanning signal line 52 with the data signal line 53, a TFT 54 is disposed as a switching element connected to the pixel electrode 51. The scanning signal line 52 is connected to a gate electrode of this TFT 54, and a scanning signal input into the gate electrode drives and controls the TFT 54. The data signal line 53 is connected to a source electrode of this TFT 54, and a data signal is input into the source electrode of the TFT 54. To a drain electrode of the TFT 54, a drain lead-out wiring 55 is connected. Through the drain lead-out wiring 55, one electrode (storage capacitor upper electrode) 55a constituting a storage capacitor element is, and through the storage capacitor upper electrode 55a and a contact hole 56, the pixel electrode 51 is connected to the drain electrode. A storage capacitor wiring 57 serves as the other electrode (storage capacitor lower electrode) constituting the storage capacitor element.
FIG. 17 is a cross-sectional view schematically showing a cross-section of the active matrix substrate taken along line X-X′ in FIG. 16.
In FIG. 17, a gate electrode 62 connected to the scanning signal line 52 is formed on a transparent insulating substrate (insulating substrate) 61 such as a glass substrate and a plastic substrate. The scanning signal line 52 and the gate electrode 62 are formed of a film of a metal such as titanium, chromium, aluminum, and molybdenum, a film of an alloy of such metals, or a stacked film of such films. The storage capacitor wiring 57 constituting the other electrode (storage capacitor lower electrode) constituting the storage capacitor element is made of the same material as that of the scanning signal line 52 and the gate electrode 62. Thereover, a gate insulating film 63 is formed. The gate insulating film 63 is formed of an insulating film such as a silicon nitride film and a silicon oxide film. Thereon, a high resistance semiconductor layer 64 made of amorphous silicon, polysilicon, and the like, and a low resistance semiconductor layer which is made of n+ amorphous silicon into which impurities such as phosphorus are doped and constitutes a source electrode 66a and a drain electrode 66b, are formed to overlap with the gate electrode 62. The data signal line 53 is formed to be connected to the source electrode 66a. The drain lead-out wiring 55 is formed to be connected to the drain electrode 66b. The drain lead-out wiring 55 is extended to be connected to the storage capacitor upper electrode 55a. The pixel electrode 51 is connected to the storage capacitor upper electrode 55a through the contact hole 56, and further connected to the drain electrode 66b through the drain lead-out wiring 55. The data signal line 53, the drain lead-out wiring 55, and the storage capacitor upper electrode 55a are made of the same material. A film of a metal such as titanium, chromium, aluminum, and molybdenum, a film of an alloy of such metals, or a stacked film of such films may be used. The pixel electrode 51 is formed of a conductive film with transparency such as an ITO (indium tin oxide) film, IZO (indium zinc oxide) film, a zinc oxide film, and a tin oxide film. The contact hole 56 is formed to penetrate an interlayer insulating film 68 formed to cover the upper surface of the data signal line 53, the TFT 54, and the drain lead-out wiring 55. Examples of materials for the interlayer insulating film 68 include acrylic resin, silicon nitride, and silicon oxide. Japanese Kokai Publication No. Hei-09-152625, hereinafter referred to as Patent Document 2, discloses an active matrix substrate having the structure shown in FIGS. 16 and 17, for example.
In the active matrix substrate having such a structure, the storage capacitor wiring (storage capacitor lower electrode) 57 is formed in the same step as a step of forming the scanning signal line 52, and the storage capacitor upper electrode 55a is formed in the same step as a step of forming the data signal line 53 and/or the drain lead-out wiring 55, in order to simplify the production processes and reduce production costs. If the pixel electrode 51 is formed on the interlayer insulating film 68 as shown in FIG. 17, the pixel electrode 51 can overlap with each of the signal lines 52 and 53. Therefore, the aperture ratio can be increased and an effect of shielding an electrical field from each of the signal lines 52 and 53 to the pixel electrode 51 can be obtained. As for connection between the pixel electrode 51 and the drain electrode 66b, the contact hole 56 is formed in the interlayer insulating film 68 above the storage capacitor wiring 57 pattern or the scanning signal line 52 pattern, and thereby the pixel electrode 51 is connected to the storage capacitor upper electrode 55a. As a result, the pixel electrode 51 is electrically connected to the drain electrode 66b through the drain lead-out wiring 55. The contact hole 56 may not be necessarily positioned above the storage capacitor upper electrode 55a, and may be positioned above the drain lead-out wiring 55. However, if the contact hole 56 is formed on the storage capacitor upper electrode 55a above the storage capacitor wiring 57 pattern as shown in FIG. 16, further reduction in the aperture ratio can be prevented.
The storage capacitor wiring of the active matrix substrate as shown in FIGS. 16 and 17 needs to be configured to have a specific value or more of Ccs/Clc that is a ratio of a liquid crystal capacity Clc to a capacity of the storage capacity element Ccs in order to secure the functions of the storage capacity element. Therefore, if the insulating film between the storage capacitor upper electrode and the storage capacitor wiring is made of one material and have an uniform thickness, the region where the storage capacitor upper electrode overlaps with the storage capacitor wiring needs to secure an area above a certain level, and thereby the storage capacity is secured to some extent. However, if a method of increasing the line width of a part of the storage capacitor wiring is used for securing the storage capacity for increase in the area of the region where the storage capacitor upper electrode overlaps with the storage capacitor wiring, the aperture ratio is reduced. In the active matrix substrate used in the liquid crystal display device, the area of the transmissive region through which an electromagnetic wave in the optical region passes, and the aperture ratio that is a proportion of the area of the transmissive region relative to the pixel are extremely important for securing display brightness.
For this problem, a method of decreasing a distance (SD gap) Lsd between the data signal line and the storage capacitor upper electrode may be mentioned as a method of increasing the area of the storage capacitor element without reduction in aperture ratio. In such a case, a short circuit attributed to a film remainder of a resist used for data signal line and storage capacitor upper electrode patterning is easily caused between the data signal line and the storage capacitor upper electrode, which reduces the production yield. Therefore, the SD gap can not be easily decreased to below a specific distance.
Therefore, a structure in which the storage capacitor wiring has a large line width is conventionally used for securing the capacity of the storage capacitor element and the aperture ratio is sacrificed. In such a structure, the line width is larger than needed in terms of a wiring resistance. Therefore, the wiring width needs to be reduced. For example, the storage capacitor wiring (auxiliary capacitor wiring) described in FIGS. 11, 13, and 14 of Japanese Kokai Publication No. 2004-78157, hereinafter referred to as Patent Document 3 partly has a line width larger than a line width needed in terms of the wiring resistance because the storage capacity between the storage capacitor wiring and the storage capacitor upper electrode (auxiliary capacitor electrode) needs to be secured to some extent.
Therefore, the aperture ratio needs to be improved by decreasing the wiring widths of the storage capacitor upper electrode and the storage capacitor wiring, the wiring widths being increased for securing the storage capacity, thereby reducing a light-shielding region. In such a respect, there was room for improvement.
Japanese Kokai Publication No. Hei-11-52418, hereinafter referred to as Patent Document 4, discloses a technology in which an extending portion of a storage capacitor wiring (auxiliary capacitor wiring) is formed along the outer periphery of a pixel electrode in a configuration in which the pixel electrode is directly connected to a drain electrode. However, in a configuration in which the pixel electrode is formed on an interlayer insulating film, the aperture ratio is improved by disposing a data signal line and the like along the outer periphery of the pixel electrode. Therefore, in such a configuration, the technology can not realize further improvement in aperture ratio.